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Stars and mentions · Last 30 days, Oct 5 – Nov 3
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A repository earns an award for finishing first, second or third in a completed trending day or week, ranked by new stars, new forks or pull request authors. Awards follow a repository through renames and transfers and count toward its current owner. Weeks run Monday to Sunday, UTC.
Mentions
USB PHYはGOWINのだろってツッコミが入ったので、USB PHYも作っときました。 正確にはPCSがGOWINの暗号化コアから自前実装になりました。 PMAはハードマクロなのでインスタンス化と動作時のパラメータ設定部分をGOWINが生成するものから自前のモノに置き換えました。 github.com/ciniml/fpga_samples/tree/main/rtl/usb3
SLogic16U3のピン配置は解析してUSB3.0で420MB/sで動くロジアナのデザインもう作って公開してあるよ。USB3 PHYもちゃんとあるよ。 github.com/ciniml/fpga_samples/tree/main/eda/slog… github.com/ciniml/fpga_samples/tree/main/rtl/usb3
TangPrimer20KでRISC-Vコア入れてLinux動かすやつは公開してあります。CPUはめっちゃ適当なので超おそいです。 ciniml/cpu_riscv_veryl
stackchan-idf v0.15.0-alpha.5にあいうえお検出実装してみた。やっぱある程度学習が必要そうだな。手元ではかなり精度よくなったけど、他の人の声でどうかきになる。 github.com/ciniml/stackchan-idf/releases/tag/v0.1…
共立になんか入荷されたな。 Chiselで書いてたAtom/Module Display用のFPGAデザインをVerylに移植して調整しなおしてます。 安定性とか改善するといいな… github.com/ciniml/atom_display_fpga/tree/feature/…